ADP5041
Data Sheet
Rev. 0 | Page 28 of 40
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to, and exit from, the PSM
mode. The PSM current threshold is optimized for excellent
efficiency over all load currents.
Short-Circuit Protection
The buck includes frequency foldback to prevent current
runaway on a hard short at the output. When the voltage at the
feedback pin falls below half the internal reference voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.
Soft Start
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a drop in input voltage, or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
LDO SECTION
The ADP5041 contains two LDOs with low quiescent current
that provide output currents up to 300 mA. The low 10 糀
typical quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.
The LDOs operate with an input voltage range of 1.7 V to
5.5 V. The wide operating range makes these LDOs suitable for
cascade configurations where the LDO supply voltage is provided
from the buck regulator.
Each LDO output voltage is set though external resistor
dividers, as shown in Figure 103. VFB2 and VFB3 are internally set
to 0.5 V. The output voltage can be set from 0.8 V to 5.2 V.
LD01, LD02
R
A
R
B
VIN2, VIN3
VOUT2, VOUT3
VOUT2,
VOUT3
FB2, FB3
C7
2.2礔
Figure 103. LDOs External Output Voltage Setting
The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with small ceramic 1 糉 input and 2.2 糉 output capacitors.
LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.
SUPERVISORY SECTION
The ADP5041 provides microprocessor supply voltage super-
vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be monitored
and corrected with a watchdog timer.
Reset Output
The ADP5041 has an active low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail that is no higher than 6 V. The
resistor should comply with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the nRSTO pin. A 10 k?resistor is
adequate in most situations.
The reset output is asserted when the monitored rail is below
the reset threshold (VTH) or when WDI is not serviced within
the watchdog timeout period (tWDI). Reset remains asserted for the
duration of the reset active timeout period (tRP) after the monitored
rail rises above the reset threshold or after the watchdog timer
times out. Figure 104 illustrates the behavior of the reset output,
nRSTO, and it assumes that VOUT2 is selected as the rail to be
monitored and supplies the external pull-up connected to the
nRSTO output.
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